12. Microcomputers and busses

Computer Based Measuring Techniques

Bengt.Lindgren@Fysik.uu.se
30-Jan-01
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Figure 12.1: Block diagram of a computer

The internal structure of computers involve several parallel communication paths, called busses (Figure 12.1), A typical bus system contains a large number of long parallel conductors in the following substructure: (1) A data bus carries the 1's and 0's representing the data to be transmitted between devices. (2) An address bus contains a number representing the destination. (3) A control bus serves as an administrator the process and also transmits instructions from the controller. Before looking into a typical bus interface more in detail (Figure 12.5) we recall some digital electronics basics.

Figure 12.2: Tri-state and Open Collector logic.

In general one may not connect the outputs from two devices to each other, unless the output circuit is of "Open Collector" or "Tri-state" type. In Tri-state logic, the output is activated or isolated (like a switch) with a third signal. The output of the leftmost device is enabled when the gate is high. An "inverting ring" on the gate of the second circuit, indicates that the enabling of the output is active when the signal is low. Only one output may be active at the time and this is usually controlled by the address and control busses.

Open collector circuits are not able to drive the high logic state by themselves, only to sink the output to low voltage. If any output is low the bus line will be in the low state independent of the other outputs. A high state is only possible when all outputs are "high" and the high voltage of the bus line is driven by a "pull-up" resistor to e.g. +5V. The open collector logic is often called "wired or" since the true state (active state or 1's) are represented by 0 V (inverted logic). It is particular useful for handshaking: Each device acknowledge an instruction by releasing the bus line but this goes high first after all devices has given their acknowledge.

Latch and registers

are used for receiving or transmitting data on the bus. Several D-flip-flops in parallel have a common clock (or gate) input and tri-state enable input.

Figure 12.3 shows a '573 octal D-type latch with tri-state outputs. 8-bit of parallel data (byte) is clocked from the inputs when C is high (1) and is present on the outputs when is low (0).

The term "latch" strictly refers to a transparent latch, whose output follow the respective inputs while enabled. A so-called edge-triggered latch ('574), with edge-triggered clock, is properly called a D-type register. The difference may have important consequences when latching data from a bus, because of the relative timing of data and the strobing clock pulse.

Figure 12.3: '573-register

Address Decoder

Figure 12.4 shows one example of a decoder circuit often used for address decoding. The output (Yn), corresponding to the address given by the number n=CBA in binary form, is low (as indicated by the rings) while all other outputs are high.

The '138 circuit has 3 extra gate-inputs which may be used to extend the address range beyond the 3 bits (C,B,A).

Figure 12.4: '138 address decoder

Figure 12.5: An example of bus connections based on the ISA-bus structure.

Figure 12.5 shows an example of how an interface to a computer bus looks like. It is based on the signals available on the ISA-bus, found in IBM PC/AT, 386, 486, 586 etc. (ISA = Industry Standard Architecture, a de facto standard). It is probably the most common bus for plug cards in measurement systems and is described later in more detail. In Figure 12.5 only the three least significant address bits are shown. The other address bits may control the gate inputs G1, G2 and GL on the '138-decoder, through additional logic.

When the computer writes data to a card or device on the bus, it puts the 8 bit (1 byte) parallel data on the data bus while simultaneously putting the address on the address bus. When address and data is available it sends a strobe signal which goes low for slightly longer than 0.5ms. During this strobe pulse the card with the appropriate address must "latch" or catch the data in a register. When the address is 5 in Figure 12.5, Y5 is 0 on the '138. Y5 and are NOR'ed to the clock of the left '573-latch. Hence this clock input becomes 1 only when =0 and Y5=0 (NOR works for active low inputs like AND for active high inputs). The output of the latch is continuously showing the values of the D-flip-flops in the '573, since is tied to ground.

When the computer reads data from the bus it sends an address and a strobe signal which goes low for slightly longer than 0.5ms. During this strobe pulse the addressed card is allowed to put its data on the data-bus, but not otherwise. As before Y5=0 for the address 5 and this is OR'ed with =0 to give =0 on the right '573 latch which then enables its tri-state outputs. We assume that the inputs to this latch is not changed during this time and that the clock (C) gate can be tied to +5V for simplicity.

When LS, HC or HCT gates (e.g. 75LS573) are used, there is no problems with the propagation time in the gates relative to the length of the strobe pulses.

The popular ISA bus, or equivalent IBM-AT-bus, is an extension of the IBM-PC bus . The original PC cards required a 60-connector socket. The ISA bus (Table 1) added a 36 connector extension socket with additional data (8), address (4), interrupt (5) and other lines. In this way the original PC-cards can also be used on the ISA bus and many I/O-cards today are only using the PC bus signals and connector. In 1988 yet another connector was added and the Extended Industry Standard Architecture (EISA) was introduced. It uses a two-level socket where the lower part follows the 60+36 ISA setup, while the upper part connects with a third set of contacts. Thus standard ISA plug-in boards can be plugged into EISA getting normal ISA functionality while EISA designed systems support 32-bit data transfers at higher rates, 32-bit memory addressing, multiple bus masters, programmable level or edge-triggered interrupts and automatic board configuration.

From the first IBM PC up through the first PS/2 computers (introduced in 1987) a computer had one bus and all of its devices and chips ran at the same speed. On those systems, additional computer memory was often added by plugging an adapter card into the same slots that held I/O adapters. Starting with machines that used the 386 CPU, the memory and CPU of the system ran faster than the I/O devices. The solution was to separate the CPU and memory from all the I/O. Today, memory is only added by plugging it into special sockets on the main computer board. In a modern PC, there may be a half dozen different Bus areas. There is certainly a "CPU area" that still contains the CPU, memory, and basic control logic. There is a "High Speed I/O Device" area that most often is a PCI Bus, connecting the high speed bus on the mainboard to the display adapter and IDE disk interface chip. Then one or two extra I/O slots may allow adapter cards to connect to the PCI bus. The remaining I/O device slots support standard "ISA" bus cards. Some computers will also provide sockets for a number of PCMCIA "credit card" adapters commonly found in laptop computers. More about these buses in section 12.5.

There are three different methods to transmit data between a card on the bus and memory:

a) Programmed I/O. Data goes via the CPU-registers. Uses the assembler instructions IN and OUT. In TurboPascal these are called by using the predefined array PORT[ ], in Borland C (or Turbo C) by the OUTPORTB and INPORTB- instructions and in Visual C++ by _outp and _inp. Addresses refer to the "port" address on the bus, see Table 2, which is distinguished from memory addresses on the ISA bus by AEN=0. This signal must be included in the address decoder on the card. The Centronics printer port uses this type of I/O.

b) DMA - Direct Memory Access. A smarter device can transfer data directly to memory without the use of the CPU. DMA is requested from the CPU on a special bus line DRQ. The CPU leaves the control of memory addressing, handshaking, etc. to the memory card. In the PC/AT there is a special DMA controller chip which simplifies the construction of the measuring card. A program stores into the DMA circuit a starting memory buffer address and length. When the device is ready for more data, it uses one bus cycle to send a request to the DMA chip, the chip then substitutes for the CPU in generating the next buffer address to the memory circuits to fetch the next chunk of data for the device. However, that first signal from the device to the DMA chip takes one more bus cycle than ordinary Programmed I/O. Thus DMA has not been attractive for disk, LAN, and other performance critical I/O.

c) Memory mapped I/O. A measuring card may be placed as part of free RAM then using and strobe pulses instead of and . This technique is used by certain commercial measuring cards to PC:s. Monitor interfaces and frame-grabber cards, connected to CCD-cameras (TV-cameras), often have their own memory which from the programmers point of view just looks like the usual memory. Data is accessed by using pointers like any other variable in the program. The graphics card of the IBM-PC is placed in memory location above 640 kbyte which is the reason why standard DOS programs are limited to 640k memory usage. Older NU-bus based Macintosh computers use this type of I/O with the upper 64 Mbytes of the 32 bits address range reserved for plug-in cards.

Table 1: ISA bus signals and pin assignments

Signal name	Pin #	Function
D0-D7	A9-A2	Data
A0-A19	A31-A12	Address lines (A0-A9 for external I/O)
AEN	A11	Address Enable - high at DMA (Direct Memory Access), low at "programmed" I/O
	B14	I/O read strobe - computer reads data
	B13	I/O write strobe - computer writes data
	B12	Memory read strobe
	B11	Memory write strobe
IRQ3	B25	Interrupt request (Serial port 2)
IRQ4	B24	Interrupt request (Serial port 1)
IRQ5	B23	Interrupt request (Parallel printer port 2)
IRQ6	B22	Interrupt request (Floppy disk adapter)
IRQ7	B21	Interrupt request (Parallel printer port 1)
IRQ9	B4	Interrupt request (PC bus IRQ2). Rerouting to INT 10
RESET DRV	B2	Power-on reset
DRQ1-DRQ3	B18,B6,B16	DMA request
-	B17,B26,B15	DMA acknowledge
	B19
ALE	B28	Address latch enable
CLK	B20	Bus clock (8.3 MHz)
	A1	I/O parity error indicator
	A10	Lengthens the read/write strobe time by up to 2.5 ms
OSC	B30	14.31818 MHz signal used for color graphic boards
T/C	B27	DMA terminal count
0WS	B8	0-wait state indicator
GND	B1,B10,B31	signal and power ground
+5V DC	B3,B29
+12V DC	B9
-5V DC	B5
-12V DC	B7
16 bit AT expansion slot
D8-D15	C11-C18	data
SBHE	C1	System bus high enable, indicates high byte on the bus
LA17-LA23	C8-C2	Extra address bits 17 to 23
	C9	Memory read strobe
	C10	Memory write strobe
	D1	Memory chip select 16 for 16 bit memory operation
	D2	I/O chip select 16 for 16 bit data operation
IRQ10-IRQ12	D3-D5	Interrupt request, rerouted trough IRQ2, spare
IRQ14	D7	Interrupt request, rerouted trough IRQ2, hard disk
IRQ15	D6	Interrupt request, rerouted trough IRQ2, spare
DRQ0	D9	DMA request
	D8	DMA acknowledge
DRQ5-DRQ7	D11,D13,D15	DMA request
-	D10,D12,D14	DMA acknowledge
+5V DC	D16
	D17	Gain master control
GND	D18	Ground

Table 2: I/O port addresses (with AEN=0) for IBM PC/AT

Hex Range	Device	Usage
000-01F	DMA controller 1, 8237A-5	System
020-03F	Interrupt controller 1, 8259A	System
040-05F	Timer, 8254-2	System
060-06F	Keyboard I/O	System
070-07F	Real time clock, NMI mask	System
080-09F	DMA page register	System
0A0-0BF	Interrupt controller 2, 8259A	System
0C0-0DF	DMA controller 2, 8237A-5	System
0F0.0FF	Math Coprocessor	System
1F0-1F8	Fixed Disk	I/O
200-207	Game	I/O
278-27F	Parallel printer port 2	I/O
2F8-2FF	Serial port 2	I/O
300-31F	Prototype card	I/O
360-36F	Reserved	I/O
378-37F	Parallel printer port 1	I/O
380-3AF	SDLC, 1-2	I/O
3B0-3BF	Mono display printer adapter	I/O
3C0-3CF	Reserved	I/O
3D0-3DF	Color Graphic monitor adapter	I/O
3F0-3F7	Floppy diskette controller	I/O
3F8-3FF	Serial port 1	I/O

Figure 12.6: ISA bus I/O write and read cycle. Note that valid data is available after has gone low in the write cycle. The output of a transparent latch will have a glitch (wrong bits during a short time), while this is avoided by using a positive edge triggered register.

Figure 12.7:
ISA card

12.1 CPU Central Processing Unit

Among the devices that control the bus, the CPU or microprocessor is the master. The interface bus itself continues inside the CPU chip but there are also internal busses that connect various components (see Figure 12.1).
- Register - very fast one-word memories. Defines the size of a "word". See.Table 3.
- Flags - 1-bits flip-flops. Keeps track of operation conditions.
- Counters - such as program counters indicating next memory location of instructions).
- ALU Arithmetic Logic Unit (+ - AND OR, ...)
- Cache memory
- Control logic and instruction decoders.

An assembler instruction (“machine language”) is as a binary number which cause a certain action determined by the instruction decoder in the CPU. The example below illustrates the same program line in different languages. Figure 12.8 illustrates how a binary number can be decoded to e.g. move data from one register to another.

Pascal  if n=m then n := n+1;
C       if ( n == m ) ++n;
Fortran if ( n .eq. m ) n=n+1
Assembler  #LINE#3:
     CS:0317  8B46FE   mov   ax, [bp-02]
     CS:031A  3B46FC   cmp   ax, [bp-04]
     CS:031D  7503     jne   #LINE#4
     CS:031F  FF46FE   inc   word ptr [bp - ds 6E07]
     #LINE#4

Note that the CPU register names, size and organization must be known together with the instruction set when programming in assembler language.

Table 3: Intel 8086 CPU-family (PC/AT) registers.

Register name			Uses in TurboPascal or C (DOS-applications)
AX	AH	AL	Calculations, I/O, return values from functions, etc.
CX	CH	CL	String counters, shift operations etc.
DX	DH	DL	Calculations, I/O, and more
BX	BH	BL	Addressing
SP			Stack pointer
BP			Base pointer
SI			Source index - points to strings in the program code.
DI			Destination index - for strings
ES			Extra segment
CS			Code segment - for program code and constants
SS			Stack segment - stack position (local variables)
DS			Data segment - position of global variables
IP			Instruction pointer
Flag			Status word

Intel 8086/8 (IBM-PC) has 16 bit registers, only allowing 2¹⁶ = 64 Kbytes direct addressing. 1 Mbytes (20 bit) is addressed using a segment and an offset address. DOS program data arrays in Pascal and C are limited to one 64k segment each. With the 80386 CPU and later, registers are 32 bit long but can also be used as 16-bit units for compatibility reasons.

Figure 12.8: Demonstration of how an instruction in form of a binary number moves data from one register to another. The two leftmost digits are decoded to enable the output of register D, while the right half of the instruction word enables the input gate of register B.

Motorola's MC 68000 - family is together with the INTEL 8086-family the most popular microprocessors today. The old Macintosh (not PowerMac) is based on the Motorola processor while the PC's (486, Pentium,..) uses INTEL-processors.

Some MC 68000 features:
32 bit general purpose data and address registers (Figure 12.9).
Address space 4 Gbytes with 32 bit address.
Only memory mapped I/O - interface cards are placed as part of free RAM.

Bus-signals for MC 68008:
A0 - A19   20 address lines (1 Mbytes)
despite 32 bit registers.
D0 - D7   8 data lines
AS', DS', R/W' strobe lines
DTACK'   acknowledge (handshaking)
IPL0-IPLK2'   3 interrupt lines

NOTE! This is the microprocessor bus, not the backplane bus in the Macintosh.

Figure 12.9: 68000/8 registers

Electronic constructors use today more likely microcontrollers than microprocessors, since these already contains I/O-ports and perhaps DAC, ADC, etc. on the same chip. Many of these are found in household electronics such as washing machines, microwave oven, CD-players, TV, videos, .....

12.2 Memory:

The memory size of a chip is given in kbit or Mbit while memory addressing is referring to bytes. Each bit in a data word is stored in separate chips or memory banks activated by the same address.

Introduced in the early 1950s, core memory consisted of small magnetic rings, that could receive two state of magnetization. Now it has been abandoned in favor of semiconductor RAM. These are (unlike cores) volatile - they loose the information when power is turned off.

RAM	Random Access Memory
SRAM	Static RAM - "D-flip-flops"
DRAM	Dynamic RAM - "capacitor charge", must be updated regularly. See Figure 12.10.
ROM	Read Only Memory - programmed when manufactured.
PROM	Programmable ROM - burns off "wires" in a matrix.
EPROM	Erasable PROM - charges that may be erased with UV-light.
EEPROM	Electrical EPROM - erased where it is connected but all bytes are erased at once.
CDROM	600 Mbyte / 5" (1993) - rather an external memory like a harddisk.
WORM	Write Once Read Many times
Flash	"EEPROM" - block wise erase.

To quote the size of DRAM chips is hazardous since it easily makes the text out of date. In 1995 the chip size used for PC-computers were 4 Mbit. 64 Mb were soon in mass production, a number which increases by a factor of 4 each second year. Research institutes produced already 1Gb memories. The limitations are set by the line size (now 0.25 mm) and electron tunneling.

Figure 12.10: A simplified DRAM element

Figure 12.11: Schematic connection of a memory to the computer bus.

12.3 Interrupt

At an interrupt ("avbrott") the running program is interrupted and the execution of an "interrupt service routine" (ISR) is started. When this program is ready the execution of the original program is continued. Example: When the mouse (or other pointing device) is moved an interrupt is generated by the mouse interface. The computer jumps to a memory resident mouse driver program, usually installed at start-up, and the cursor is redrawn on the screen. Then the execution of the original program is continued.

In many measuring situations data are not coming regularly in time, e.g. for radioactive decays. Instead of having the computer locked up waiting for data, the data can generate an interrupt. The running activity (e.g. plotting) is interrupted and an ISR-program reads and stores the data.

PC/AT:

A special interrupt controller circuit 8259 PIC (programmed interrupt controller) simplifies the interrupt handling versus the CPU.

1. IRQn goes high.

2. If bit number n is =0 in a mask register in the 8259 PIC (port-address hex. 21) an interrupt is requested at the CPU.

3. The program counter is saved by the CPU on the stack memory. The program counter is a register in the CPU showing where the next instruction is in the memory.

4. The program counter is replaced by the interrupt vector n. This vector contains the start address for the ISR-program. The interrupt vectors are placed in the beginning of RAM with memory addresses hex. 20 + 4n (byte).

5. The ISR-procedure must first save on the stack all CPU-registers it may use itself, so no values are changed for the interrupted program. These instructions are automatically inserted by the TurboPascal or Borland C compiler when a procedure or function has the key-word Interrupt

6. The ISR-procedure performs its task.

7. The ISR-procedure informs the 8259 PIC that it is ready by writing hex. 20 to a register with the port-address hex. 20: outportb(0x0020,0x20); in BorlandC.

8. Reset all CPU-registers. Automatically inserted instructions at the end; of an Interrupt - specified procedure.

9. The program pointer is restored by the CPU and the old program continues.

Installation of an ISR-procedure (see program example):

1. Write the address of the ISR-procedure to the interrupt vector n.
setvect(n+8, isr); in BorlandC.

2. Reset bit n to 0 in the 8259 PIC:s mask register in order to activate the interrupt n.
outportb(0x21, inportb(0x21) & (~(1 << n)) ); in BorlandC.

In the following program example a variable k is incremented in the isr-procedure/function for each hardware interrupt #7. The value is printed on the screen continuously by the main program.

Interrupt program example in Borland C:

/* C-program interrupt_test */
#include <stdlib.h>
#include <stdio.h>
#include <conio.h>
#include <dos.h>

unsigned int k;   /* global variables */

void interrupt isr(void) {
    k++;
    outportb(0x0020,0x20); /* non specific EOI to 8259 PIC  */
}

void main(void) {
/* Set interrupt vector entry to isr-procedure
   IRQ7 interrupt line correspond to 7+8 dos interrupt number */
   setvect(7+8, isr);

/* Enable interrupt:
   Get IMR (interrupt mask register) from 8259 and clear mask bit 7 */
   outportb(0x21, inportb(0x21) & (~(1 << 7)) );

   do {   printf("%10u\n",k);   } while (!kbhit());

/* Disable interrupt:
   Get IMR (interrupt mask register) from 8259 and set mask bit 7 */
   outportb(0x21,inportb(0x21) | (1 << 7));

}  /* main */

Interrupt program example in TurboPascal:

program interrupt_test;
Uses  Dos,Crt;
var k:word;

procedure isr;
interrupt;
begin
   k:=k+1;
   port[$20]:=$20;   {non specific EOI to 8259 PIC}
End; {isr}

begin
(* Set interrupt vector entry to isr-procedure.    IRQ7 interrupt line correspond to 7+8 dos interrupt number *)
   SetIntVec(7+8,@isr);    (* Equivalent to:
                              MemW[$0000: (7+8)*4 ] := Ofs(isr);
                              MemW[$0000: (7+8)*4+2] := Cseg; *)
(* Enable interrupt:
   Get IMR (interrupt mask register) from 8259 and clear mask bit 7 *)
   port[$21]:=port[$21] and (not (1 shl 7) );

   repeat  writeln(k:10);  until keypressed;   (* main program part *)

(* Disable interrupt:
   Get IMR (interrupt mask register) from 8259 and set mask bit 7 *)
   port[$21]:=port[$21] or (1 shl 7);
end.

The ISA bus use edge sensitive triggering, which avoids the problem of retriggering for long interrupt pulses. However, most other systems use level sensitive triggering, which allow several units to use the same IRQ-line with open collector logic. Different methods are used to determine which device that caused an interrupt:

1) Polling "Autovectored polling" (compare SPOLL in GPIB).
- IRQ (interrupt request) to the CPU.
- Read successively each status register on each connected unit. A flag indicates whether the unit requested interrupt or not.
- To each unit there is an interrupt vector, then continue as described for the PC-interrupt.
- The IRQ-line is low until all units, requesting an interrupt, has been served and released the IRQ-line..

2) Vectored interrupt "full vectored interrupt acknowledgment protocol"
- IRQ to the CPU
- CPU gives an "interrupt acknowledge" (INTA)
- The interrupting unit writes its interrupt vector on the data bus lines, then as for the PC.
This is the method used by IBM PC/AT but simplified for the user, thanks to the 8259 PIC-circuit)

Several units may be connected in a so called "Daisy chain". Interrupt acknowledge is here not a bus signal but goes into one unit which (by some logic) sends it to the next unit unless it requested an interrupting by itself. The unit closest to the CPU gets the highest priority.

Figure 12.12: Daisy chained vectored interrupt system where the interrupting units are sending an identification code. The device closest to the CPU has the highest priority but passes the interrupt acknowledge (INTA) signal to the next device when it did not request interrupt itself. Upon receiving INTA the second device puts its interrupt vector on the data bus.

12.4 Digital signal transmission

Microprocessor-based systems are continuing to increase in frequency of operation at an accelerating pace. As a result, local and external busses are also being pushed to higher and higher frequencies. Time allowed for signal "settling" can no longer just be guessed and the bus design must be optimized for minimal data transfer time. This in turn requires that phenomena such as reflections, crosstalk, ground shift, etc., be understood and minimized.

Reflection in transmission line networks are basically the result of impedance discontinuities. The common coax-cable RG-58 has a "characteristic impedance" of 50 W, meaning that a wave front moving along the line has a voltage / current ration of 50 W. For a lossless line (negligible Cu-resistance) the impedance, which is resistive (real), is , where L = inductance and C = capacitance per unit length. The transmission velocity is about 2/3 of the velocity of light or about 1 meter in 5 ns. If the receiving end has a low impedance (R_L=0 in fig.) the wave is reflected with opposite phase so that the sum of incoming and reflected voltage is zero in the shorted point. If the impedance is high (R_L=¥) the summed currents must be zero and the wave is reflected with the same voltage phase. 50W-termination gives no refection.

Figure 12.13: Characteristic impedance of a cable and termination.

The characteristic impedance on printed boards and for twisted pair cables is about 100 W. The type of bus transmission line together with driver and receiving circuits (transceivers) determines the maximum speed and length for the digital transmission on the bus. There are often special driver and receiver chips constructed for different bus-types.

12.5 Other parallel backplane busses

A "backplane" (or motherboard) is used to electrically interconnect a group of circuit boards while providing mechanical support for those boards in a rack or computer box. The connectors (or slots) of a backplane bus are usually wired in parallel. Table 4 list some popular busses and their characteristics.

Table 4: Backplane busses

Bus	Band-width Mbyte/s	Data width	Address width	Sync or Async	IRQ lines	Drivers	Comments
PC/XT	1.2	8	20	S	5E	TTL	IBM PC & compatible
PC/AT	5.3	8,16	20,24	S	10E	TTL	Industry Standard Architecture (ISA) but not a standard according to any standardization commission. Accepts PC/XT
EISA	33	8,16,32	20,24,32	S	11P	TTL	"Extended ISA", accepts old AT-cards but with lower speed
PCI	132	32 (64)		S		TTL	New local bus in PC-compatibles, Power Macintosh and others. For multimedia, graphics, disk drives, LAN cards and more. Plug-and-play. More info: http://www.pcwebopedia.com/PCI.htm
CAMAC	3	24	9	S	L	TTL/ OC	Instrument bus often used in nuclear and particle physics.
NuBus	40	32	32	S	M	TTL	(IEEE-1196, 1987) used in Macintosh-II. Common data and address bus. 16 slots each using 16 Mbyte of the last 1/16 of the 4 Gbyte address space.
VME	40	8,16, 32	16,24, 32	A	7	TTL	VERSA Module Eurocards, developed from Motorola's VERSA-bus. Asynchronous microprocessor bus with plenty of accessories. SUN-3
VXI							VME eXtension for Instrumentation. Fast-growing platform for instrumentation systems, in particular µ-processor based systems.
Futurebus	120			A		special	3,2 Gbyte/s? Not approved as a standard yet.
Fastbus	160	32	32	A	M	ECL	Developed for data collection and control of the large detector systems in particle and high energy physics.

E = Edge-sensitive; L = LAM ("look at me"); M = via bus mastership; P = programmable edge- or level-sensitive

Some busses use synchronous data transfer. A "strobe"-signal indicates when data is available but no "acknowledge" of received data. For asynchronous transfer an “acknowledge"-signal indicates that data has been received and until then data is available on the bus.

Sometimes a separate address bus is missing and a common data and address bus is used (e.g. NuBus in Macintosh II). In general this requires more logic on the I/O cards compared to the example in Figure 12.5.

Devices and plug-in cards for the more advanced busses are often using special ASIC (Application Specific Integrated Circuits) for the interface with the bus.

Plug and Play: ISA boards usually have to be manually configured via DIP switches and/or jumpers, e.g. to set the base I/O address. Now, with special logics on the plug-in card, one can take advantage of Plug and Play operating systems, such as Windows 95, and use software.

PCI - bus	ISA - bus
Peripheral Component Interconnect	Industry Standard Architecture
33 MHz (66 MHz ext.) "half the memory bus speed"	8 MHz
32 bit (64 bit ext.)	16 bit
133 Mbytes/s, (800 Mb/s burst transfer)	8 Mbytes/s (64 Mbytes/s)
49 signals multiplexed address and data address: memory, I/O, configuration 4 IRQ (shareable) +5V, +3.3V, +12V, -12V, GND	88 signals separate address and data lines address: memory, I/O 11 IRQ +5V, -5V, +12V, -12V, GND
5 V (3.3 V) signal level	5 V TTL-signal level
Plug-and-play defined in the standard	often jumper configuration
No DMA but "Bus mastering"	DMA

Bus connectors. Top: ISA-bus,. Bottom right: PCI (32-bit standard), left: 64 bit extension.

PC Card (PCMCIA)
The Personal Computer Memory Card International Association (PCMCIA) established a standard for credit-card sized PC plug-in interfaces. Originally used for flash memory, but now available for general-purpose and specialized I/O, such as data acquisition and instrument control. PCMCIA is now the expansion standard for notebook computers.

History http://pclt.cis.yale.edu/pclt/PCHW/BUS.HTM
In 1984 IBM was shipping its PC AT model. The CPU, memory, and I/O bus all shared a common 8MHz clock. This became the basis for all subsequent clone computers. The term "AT" is a registered trademark of IBM, so this I/O bus became known as the ISA (Industry Standard Architecture) bus. Every currently marketed PC supports some ISA interface slots. The bus and matching adapter cards are simple and cheap. ISA is a 16-bit interface, which means that data can be transferred only two bytes at a time. More importantly, the ISA bus runs at only 8 MHz and it typically requires two or three clock ticks to transfer those two bytes of data. This is not a problem for devices that are inherently slow like the COM port (modem), the printer port, the sound card, or the CD-ROM. However, the ISA bus is too slow for high performance disk access and therefore is not acceptable in Servers. It is also too slow for modern Windows display adapters.

In 1987 IBM introduced a new Microchannel (MCA) bus. It had clear advantages over the previous PC bus. It's 10 MHz clock was slightly faster. The cards could be automatically configured with a utility program instead of setting physical switches and jumpers. The bus can transfer four bytes of data at a time and, in some configurations and with some cards, it can transfer data every clock tick. However, the Microchannel itself was expensive, the adapter cards were more expensive, and the technology remained encumbered by IBM licensing. The other vendors developed an extension of the older ISA interface called EISA. An EISA slot contained the older ISA interface, and then an extra socket with additional connections. The user could plug either an old ISA card or a new EISA card into the slot. The newer cards supported a 32-bit data interface and could therefore transfer four bytes of data per operation. However, to remain compatible with the old card, EISA still ran at 8MHz. And the extra logic pushed up the cost of both the EISA system and each adapter card.

As the 486 CPU chip became popular, the idea of running I/O devices at 8 or 10 MHz collided with a mainboard that ran everything else at 33 MHz. The first solution was the VESA Local Bus (VLB), which became popular at the start of 1993. VESA is a consortium of companies making displays and display adapters. Desktop machines began to include one or two Local Bus slots to support a high speed video card and, perhaps, one other high speed device. A few vendors produced VESA SCSI adapter cards, or Local Bus LAN adapters. Nevertheless, VESA remained largely a display standard.

PCI - The Current Standard
The PCI bus was developed by Intel. Although it is mostly known for its CPUs, Intel also has a historical association with Ethernet, multimedia, and some disk interfaces. So Intel was unhappy with the VLB concentration on just the video interface and wanted to develop a general purpose bus. The objective was an interface that was fast and inexpensive. It did not have to be simple (advances in chip technology took care of that) and could achieve a low cost by high volume production.

PCI is a 64 bit interface in a 32 bit package. Figuring this out requires a bit of arithmetic. The PCI bus runs at 33 MHz and can transfer 32 bits of data (four bytes) every clock tick. That sounds like a 32-bit bus. However, a clock tick at 33 MHz is 30 nanoseconds, and memory only has a speed of 70 nanoseconds. When the CPU fetches data from RAM, it has to wait at least three clock ticks for the data. By transferring data every clock tick, the PCI bus can deliver the same throughput on a 32 bit interface that other parts of the machine deliver through a 64 bit path.

The PCI bus has all the signals of the old ISA bus. This allows a PCI adapter card to emulate older equipment. For example, a PCI disk controller can respond to the same addresses and generate the same interrupts as the older disk controllers that the BIOS understands. However, PCI devices can also be self-configuring and operate in a Plug and Play mode.

The PCI bus connects at one end to the CPU/memory bus and at the other end to a more traditional I/O bus. The PCI interface chip may support the video adapter, the EIDE disk controller chip, and maybe two external adapter cards. A desktop machine will have only one PCI chip, and so it will add a number of extra ISA only slots. A server may add additional PCI chips, and extra server slots will usually be EISA.

While ISA and EISA are exclusively PC interfaces, the PCI bus is now used in Power Macintosh systems and PowerPC machines. It may be attractive for minicomputers and other RISC workstations.

PC Card (formerly PCMCIA) and CardBus
Laptop computers typically have two slots for "credit card" adapters. Originally this interface was called "PCMCIA" but that proved too technical for wide acceptance. Today there is an effort to rename the interface as "PC Card."

A credit card adapter is much smaller than the adapter cards that plug into the ISA or PCI slots of a laptop computer. They are also more expensive and slower. Although PC Card slots have been offered as an option in some models of desktop computers, the clear disadvantage over full sized card restricts their use to laptops.

The credit card slots are bridged to the main I/O bus of the computer. Laptops have been built to use an ISA, Microchannel, or VESA Local Bus internally. The most modern laptops now come with an internal PCI bus. Credit card adapters can be connected to any of these systems.

A full sized card can come with switches or jumpers that can be used to configure its I/O address or IRQ. More advanced cards may be configured with a utility program. Since it is small project to remove the cover from a desktop system and switch cards, a desktop adapter is designed with the assumption that it will stay put.

A PC Card adapter is sealed in a metal case. It has no configuration switches. They are easy to insert and remove, since a user may need a LAN card for use in the office and a modem card for use at home or when traveling. The PCMCIA standard was developed late enough to incorporate an early version of "plug and play."

In the laptop, each socket is itself an I/O device. A PC Card adapter can be plugged into the system at any time, even when the power is on and a system is running. The socket can query the card for identifying information, and the adapter can be configured by the operating system to use available I/O addresses, IRQs and similar resources.

Full support for PCMCIA was too complicated (and required too much memory) to easily fit into the old DOS operating system. Laptops were not an important platform for Windows NT, so it has a very limited support for this architecture. The best PCMCIA support is found in Windows 95. It is possible to plug a new adapter card into a running Windows 95 machine, have the operating system recognize it immediately, and have the system dynamically configure new driver support.

The main problem with the PCMCIA bus is performance. Current systems support only a 16 bit interface to adapter cards. Adapter cards transfer data at a rather low clock speed, and there is no provision for Busmaster data transfer. The maximum data transfer rate from a PC Card adapter to the CPU or memory is only 2 megabytes per second. A PCI adapter, in contrast, can burst data at 133 megabytes per second.

A 32 bit version of PCMCIA has been created under the label "CardBus". It is currently available only on the most powerful and expensive laptop systems. If you are looking for desktop performance in a portable system, CardBus slots are highly desirable.

Current Status (1997)
Although the ISA bus may be ten years old, it remains a perfectly reasonable option for devices that do not require highest performance. The consumer-oriented products all come with built-in video and disk adapters. Those are the two components that have the greatest impact on home computers and probably most desktop business machines. There simply isn't any need for a higher speed to support the sound card on a multimedia system, and the CD ROM is the slowest storage device available.

The higher end of the consumer market and the machines sold directly to corporations typically have a few slots with a PCI interface. It is nice to have, but in the next year or so these slots may remain empty. The pre-installed devices cover most requirements, and storage expansion is simple and inexpensive using EIDE disks and devices.

A Server comes in a full sized floor standing tower. Some servers have room for 18 disk drives. There will certainly be a PCI bus, but there will also be several standard SCSI adapters to connect all the disks, tapes, and CD-ROM units. Every adapter in a dedicated Server should be a PCI card. Some SCSI controller may be built into the mainboard. An external PCI SCSI adapter can provide additional function, cache memory, or RAID support. LAN adapters should plug into the PCI slot. Because the older ISA slots are much slower, there is a strong bias that any function that is not important enough to warrant a PCI adapter is something you probably shouldn't do on a server.

Laptop computers are appearing with an internal PCI bus. This provides high speed support for the internal connection to the video and disk controller chips. It may also provide for PCI cards when the unit is connected to a docking station.

12.6 Parallel busses with "cable interface":

IEEE-488: GPIB - General Purpose Interface Bus, see separate section in this compendium.

SCSI: Small Computer System Interface ("skuzzy") - standard for connecting several disks and other units with transfer of large amount of data.
SCSI-1: 4 Mbyte/s; SCSI-2: 10 Mbyte/s (20 Mbyte/s at 32 bit transfer)
Up to 8 connected units, 6 - 25 m length depending on type of driver.
The standard also defines the system architecture (software).

Centronics: Standard connecting printers. Simple measuring and control electronics is also readily interfaced since data already is latched. Figure 12.14 shows an example of a Centronics-interface. The connector at the computer end is a 25-pin DIN-connector. Table 5 show the "port"-addresses, data-bits, pin-numbers and signal names. Some IBM-computers use the addresses (hex) 3BC, 3BD, 3BE instead of 378, 379 and 37A. For further details and examples on how to use this port, see: http://www.geocities.com/SiliconValley/Bay/8302/

Table 5: Centronics signals, pin numbers and addresses.

Pin	Name	Address (hex)	Data bit	Pin	Name	Address (hex)	Data bit
1	Strobe'	37A	0^*	10	ACKNLG'	379	6
2	Data bit 0	378	0	11	Busy	379	7^*
3	Data bit 1	378	1	12	PE	379	5
4	Data bit 2	378	2	13	Select	379	4
5	Data bit 3	378	3	14	Auto feed'	37A	1^*
6	Data bit 4	378	4	15	Error'	379	3
7	Data bit 5	378	5	16	Init'	37A	2
8	Data bit 6	378	6	17	Select in	37A	3^*
9	Data bit 7	378	7	18-25	Ground

^*) Hardware inverted by the Centronics interface.

Figure 12.14: Centronics port for PC. However, the connection of ACKNLG' to IRQ7 differs among PC:s and is often active low and level sensitive.

12.7 Serial communication

Alphanumeric communication between a computer and devices of moderate speed is most frequently done using the 7-bit ASCII code (American Standard Code for Information Interchange -see Table 8), with bit serial transmission over a single line. Wiring is simplified and in particular more convenient for long distances between computer and device. A modem (modulator - demodulator) can convert a serial bit stream to an audio signal, and vice versa, which can be sent vial telephone lines.

Although the CPU works with parallel information, data transfer may be serial by using shift registers. A shift register is a set of several D-flip-flops, with each output driving the next input, and with a common clock input (see Figure 12.15). A pulse sequence on the input is clocked, bit by bit, and the result is presented in parallel form on the output (Q0 - Q3). The opposite is also possible. Data in parallel form are loaded to the shift register and shifted out in serial form (not shown in Figure 12.15).

Synchronous serial communication use a common clock-pulse line while asynchronous communication use separate oscillators at the transmitting and receiving end. Usually the protocol then contains a "start-bit" to synchronize the data transmission and the two oscillator frequencies must only be set equal enough not to phase out the transmission of one pulse train (data package).

Figure 12.15: Principle of a shift register

RS-232 is the most common standard for serial communication and is used by terminals and measuring instruments. The original method, which dates back many decades, consists of switching a 20 mA current - "current-loop" signaling. It is now superseded by the RS-232C standard of 1969 and subsequent RS.232D of 1986. The definition of the pulse train is shown in Figure 12.16.

§ Start-bit + 7 or 8 data-bits + optional parity-bit + 1 (or 2) stop-bits.

§ Logical levels: between +3 and +15 V respectively -3 and -15 V. A data-1 is represented by the negative voltage level!

§ The LSB least significant bit is sent first of the data bits.

Figure 12.16: RS-232 serial data-byte timing waveform.

§ Asynchronous transmission is used with certain transmission speeds "baud-rates" (bit/s): 300, 1200, 2400, 4800, 9600, 19200, ... baud.

§ The start-bit is used to synchronize the transmission. The two independent oscillators at the transmitting and receiving ends need only be roughly equal so that the bits in one 7- or 8-bit data are not out of phase.

§ The parity bit is used to detect errors in the transmission. At even parity the number of data ones + the parity bit should be even, e.g. for ASCII-C (hex. 43 = 100 0011) the parity bit is set = 1 but not for A and B (100 0001 and 100 0010). Similarly for odd parity. If an incorrect parity is detected the computer may ask for a new transmission of that character.

Example: start-bit + 7 data bits + parity-bit + 1 stop-bit and 9600 baud corresponds to 960 characters/s transmission speed. One screen full of text contains about 1900 characters and takes about 2 s to transfer. Modern (1997) modems transmit data with 56K bps over the telephone lines, using special data compression. More info: http://pclt.cis.yale.edu/pclt/COMISDN/ISDNIDEA.HTM .

This is the communications configuration panel from Windows Terminal. The use of 5 bits per character was used by very early Teletype equipment that was already obsolete in the 1950's, and no device built in the last 20 years has needed more than 1 stop bit. What is Xon/Xoff Flow Control? XON and XOFF are byte values. The Teletype had a device to read punched paper tape. The XON character turned the tape reader on, and the XOFF character turned it off. Long after the last paper tape was burned, computers have maintained the tradition that XOFF can optionally mean "stop sending data," in which case XON means "begin sending again." What is parity? Before modems did error correction, parity provided a simple mechanism to detect characters corrupted by phone line noise. Today it is unnecessary and is typically disabled.

So in current use, the correct setting for the COM port is always 8-bit characters, no parity, 1 stop bit, hardware pacing (more about that later) and some speed faster that the native transmission speed of the modem.

Table 6: The 10 most important RS-232 signals (of 22) and the corresponding pin numbers on 25-pin and 9-pin connectors.

Name	Pin # (25)	Pin # (9)	Direction DTE<-->DCE	Function as seen by DTE
TD	2	3	-->	transmitted data
RD	3	2	<--	received data
RTS	4	7	-->	request to send (=DTE ready)
CTS	5	8	<--	clear to send (=DCE ready)
DTR	20	4	-->	data terminal ready
DSR	6	6	<--	data set ready
DCD	8	1	<--	data carrier detect
RI	22	9	<--	ring indicator
FG	1	-		frame (chassis) ground
SG	7	5		signal ground

Since transmission (TD-2) and receiving (RD-3) are using separate wires one is distinguishing between DTE (Data Terminal Equipment) and DCE (Data Communication Equipment) units. A terminal always looks like a DTE and a modem like a DCE. IBM PC and compatibles look like a DTE but other computers may very well look like DCE! A measuring instrument = ??? Consult its manual! "In general, two RS-232 devices, when (first time) connected together, won't work" (Horowitz-Hill p.723). To add to the confusion: Note that pin #2 (TD) on the 25-pin connector correspond to pin #3 on the 9-pin connector (Table 6). A voltmeter may sometimes help. The TD-pin is usually between -12V and -15V when no transmission occurs (see Figure 12.16), while RD is floating. Figure 12.17 shows some common ways of connecting to RS-232 devices.

Table 6 summarizes the data for RS-232 and similar standards with the same type of pulse train. RS-232 is limited to point-to-point connections between PC serial ports compared to the other improved standards. Macintosh uses RS-422. According to the RS-232C standard the maximum wire length is 15 m but with opto-couples at both ends ("korthållsmodem") much longer (km) wires may be used. The problem with different ground potentials is eliminated and an extra "safety barrier" between computer and the outside is introduced. Electric faults along the line will kill the optocouples but the computer interface may survive.

Figure 12.17: Different ways of connecting a DTE and a DCE. In particular fig b) and d) are common since only 3 wires are needed (but more often 4 with separate grounds).

Table 7: Different Serial standards

Serial data standards:	RS-232C/D	RS-423A	RS-422A	RS-485
Mode	single-ended	single-ended	differential	differential
Max number of drivers	1	1	1	32
Max number of receivers	1	10	10	32
Max cable length	15m (100m)¹	1200m	1200m	1200m
Max data rate (bits/s)	19.2k (115k)¹	100k	10M	10M
Transmit levels min / max	±5V / ±15V	±3.6V / ±6.0V	±2V min	±1.5V min
Receive sensitivity	±3V	±0.2V	±0.2V	±0.2V
Load impedance	3k - 7k	>450W	>100W	>60W
Output current limit to gnd.	500mA	150mA	150mA	150mA
Driver Z_out min (pwr off)	300W	60kW	60kW	120kW

1) Most RS-232 ports today are capable of far higher speeds and cable lengths than the rated standard.

Standard serial communication is handled by a chip, called UART (Universal Asynchronous Receiver Transmitter), which implements the required transmitting and receiving, conversion of data from parallel to serial format and vice versa, etc. The Intel 16550 UART is the standard UART found in PCs today. The 8250 UART is found in older PCs.

The RS-232 and RS-422 standards specify only full-duplex communication, which means that transmit and receive operations can take place simultaneously (separate lines). RS-485 also specifies half-duplex operation, in which a combined transmit and receive line is used - hence less wires. Devices in a half-duplex network are used in a master/slave configuration, where slaves (devices) transmit only when they are instructed to do so by a master (PC).

In process industries and similar noisy environments a 4 - 20 mA analogue instrumentation is often still used together with 20 mA current-loop digital transfer. This requires an extensive of point-to-point wiring since each sensor or instrument must have its own pair to the controlling computer.

Fieldbus - "Fältbuss"
(see http://hallen.ele.kth.se/~willi/Fieldbus.html ; http://rolf.ece.curtin.edu.au/~clive/Fieldbus/fieldbus.htm. and “Elektroniktidningen” 1, Jan.1997, p.19.)
Fieldbus is a generic-term which describes a new digital communications network which will be used in industry to replace the existing 4 - 20mA analogue signal. The network is a digital, bi-directional, multidrop, serial-bus, communications network used to link isolated field devices, such as controllers, transducers, actuators and sensors. This new standard is on the way and has been so for many years. The reason for the delay is due to the lack of an international Fieldbus protocol standard which will ensure complete interchangeability and interoperability between different suppliers. Several company constellations have been fighting each others to have their ideas (and developed chips) accepted. With consumers becoming impatient many companies have decided to released there own systems which work off different standards. Profibus is widely used in Germany and Europe while DeviceNet is mostly popular in North America. CAN (Controller Area Network http://www.kvaser.se ) is based on DeviceNet.

LAN Local Area Network
is the generic name of busses used for serial transmission with high speed between e.g. computers.

Ethernet: 10 Mbit/s, yellow thick coaxial cable with special connectors which avoids cutting the cable when a new unit is installed. From a "router" or a "hub" a group of computers are connected via "thin wire ethernet (usual coax. cable RG-58 with BNC-connectors) or twisted pair (TP). Information is sent in packages with address and data. All units may "talk", without any "chairman" - but special logic detects collisions. If the bus is busy the device waits a while and tries again. Most computers and workstations at Uppsala University are connected through ethernet. The PC-computers at "Mättekniklab" are connected with a local thin wire Ethernet.

LocalTalk (former AppleTalk) is in particular used for connecting Macintosh and printers. 230 kbit/s. Electrically as RS422 coupled to a transformer which allows both sending and receiving on the same twisted pair of wires (differential driving) but the pulse train is different. Special logic to avoid collisions.

USB (Universal Serial Bus) will replace the old RS-232 port on most PCs from 1998 for external communication with modems, instruments, mouse, keybord, etc. The USB is a "real" serial bus with 12 Mb/s speed, where up to 127 units can be connected in a plug-and-play manner.

USB 1.1

USB 2.0

RS-232

12 Mbit/s (1.5)

480 Mbit/s

19.2 kbit/s (0.9 Mb/s)

Dynamic attach - detach, address assignment.
Standard data format - "plug-and-play".
Polled bus with a host controller.
1) Token packet - with addressing (controller)
2) Data packet (by sending device)
3) Handshake packet (by receiving device).

More info: http://www.pcwebopedia.com/USB.htm and http://www.intel.com/design/usb/tour/homepage.htm

Firewire (IEEE 1394) is also a new serial bus which is supposed to take over the communication with fast units such as video signals and external data storage. The present maximum speed is 400 Mb/s but 1600 Mb/s is on the way. More info: http://www.pcwebopedia.com/IEEE_1394.htm

Table 8 : 7 bit ASCII-code for characters. Additional 128 characters are possible with the 8:th bit =1, including the Swedish åäö, but this code is not part of the standard. Email uses a 8-bit iso-8859-1 character set but "quoted printable" code for åäö is safer to use since some computers masks the 8^th bit.
The table gives the code in hexadecimal numbers.

hex

NUL

SOH

STX

ETX

EOT

ENQ

ACK

BEL

DLE

DC1

DC2

DC3

DC4

NAK

SYN

ETB

CAN

SUB

ESC

(

)

;

[

]

{

}

DEL

acronym	name	acronym	name	acronym	name
NUL	null	SOH	start of heading	STX	start of text
ETX	end of text	EOT	end of transmit	ENQ	enquire
ACK	acknowledge	BEL	bell	BS	backspace
HT	horizontal tab	LF	line feed	VT	verical tab
FF	form feed	CR	carriage return	SO	shift out
SI	shift in	DLE	data line escape	DC1	device control 1
DC2	device control 2	DC3	device control 3	DC4	device control 4
NAK	negative acknowledge	SYN	synchronous idle	ETB	end of transmit block
CAN	cancel	EM	end of medium	SUB	substitute
ESC	escape	FS	file separator	GS	group separator
RS	record separator	US	unit separator	SP	space character